Services

Our services include:

FPGA Digital Design
ASIC front-end design
Verification in simulation
FPGA emulation
Synthesis and Sign-off STA
IP core designs as well as complete SoCs
Embedded SW development – Baremetal or under OS

In past we have sucessfully designed:

Communication peripherals
Encryption accelerators
SoC infrastructure such as crossbars, clock, reset and power controllers
Analog macro controllers such as Memory controllers or analog front-end controllers

Our technical experience includes:

AMD, Intel, Microchip and other FPGA vendors
180 nm to 55 nm ASIC process nodes
Simulation with XCelium, VCS, Modelsim, Verilator, NVC and GHDL simulators
Verification with frameworks such as UVM, OSVVM, Cocotb or custom methodologies
Tools such as Design Compiler, PrimeTime, OpenROAD, OpenSTA or Yosys.
SDC constraining and Timing closure.
Contribution to open source EDA toolchains.

We use open source technologies such as:

NVC or Verilator for logic simulation
Yosys and OpenROAD for physical design
IHP 130 and Skywater 130 for low-volume ASIC design

Products

We have developed own IP cores that are open source, and you can license them for commercial usage.

CTU CAN FD

CTU CAN FD is a CAN 2.0 and CAN FD soft-IP core:

ISO 11898-1 2015 compliant
Up to 8 prioritized TX buffers and 1 RX FIFO
RX Frame filtering
ISO and non-ISO CAN FD modes
Parity support on RX and TX buffers
Custom frame corruptions and extensions for CAN bus analysis
Linux driver as kernel module or part of mainline Linux kernel

CTU CAN FD is fully verified with 100 % code coverage support in last release. Compliance to ISO 11898-1 2015 is verified using ISO 16845-1 2016 compliance test sequence. The core is used in dozens of FPGA applications in automotive, space application on earth orbit and mass manufactured ASICs.